/*********************************************************************
	\file :           os_sw_layers\bios\mcu\Mcu.c 
	\brief:           PLL initialization prototypes and functions definitions.
	\author:          Omar Ramirez
	\version:         1.0
	\date:            Wed, 12, Feb 2014 
*********************************************************************/

 
#include "Mcu.h"
 

/********************************************************************************
* \brief Turn PLL ON.
* \return             
*/
 
static void vfnPLL_On(void);

/********************************************************************************
* \brief Turn PLL OFF. 
* \return             
*/
 
static void vfnPLL_Off(void);

 
static void vfnPLL_On(void)
{
    /* PLL enabled */
    PLLCTL_PLLON = 1u;                   
              
    /* Wait until the PLL is within the desired frequency */
    while(!CRGFLG_LOCK)
    {}    
    /* Clear IPLL Lock Interrupt Flag */
    CRGFLG_LOCKIF = 1u;                  
    /* Interrupt will be requested whenever LOCKIF(IPLL Lock Interrupt Flag)is set */        
    CRGINT_LOCKIE = 1u;           
}

 
static void vfnPLL_Off(void)
{     
    /* Disable the PLL */
    PLLCTL_PLLON = 0u;     
}


void Mcu_Init( void )
{
   volatile u32 u32temp = 0;
    /* Disable PLL */
    vfnPLL_Off();  
            
    
    /* Set PLL synthesizer register */
    SYNR_SYNDIV = CNF_SYNDIV_VALUE;    
    
    /* Set PLL divider register */  
    REFDV_REFDIV = CNF_REFDIV_VALUE; 
    
    /* Configure PLL filter for optimal stability and lock time */
    REFDV_REFFRQ = CNF_REFFRQ_VALUE;
            
    /* Set Postdiv value,  */
    POSTDIV_POSTDIV = CNF_POSTDIV_VALUE; 
    
    /* Configure VCO gain for optimal stability and lock time */
    SYNR_VCOFRQ = CNF_VCOFRQ_VALUE;   
          
    /* Clock Monitor Enable. This is required to enter Self Clock Mode */
    PLLCTL_CME = 1u;   
                      
    /* Self Clock Mode Enable, If CME & SCME are both asserted and the Clock Monitor
    in the oscillator block detects a loss of clock, Self Clock Mode will be entred */
    PLLCTL_SCME = 1u;          
              
    /* Clear Self Clock Mode Interrupt Flag */                                                                          
    CRGFLG_SCMIF = 1u;          
             
    /* Interrupt will be requested whenever SCMIF(Self Clock Mode Interrupt Flag) is set */ 
    CRGINT_SCMIE = 1u;        
                
    /* Enable PLL and wait for locking */
    vfnPLL_On();    
}


void Mcu_InitClock( void ) 
{
     
}

void Mcu_DistributePllClock( void ) 
{
  #ifdef CNF_PLL_AS_CLOCK_SOURCE
    /* Select PLL as clock source */
    CLKSEL_PLLSEL = 1u;  
  #endif
}

/*********************************************************************
	File	: os_sw_layers\bios\mcu\Mcu.c 
*********************************************************************/
